In a new study published May 27 in the journal Nature, scientists found a way to cram more computing power into a chip by stacking silicon circuits in multiple layers in a way that doesn't impact performance.
The researchers' 3D chip uses ultrathin silicon membranes and low-temperature manufacturing techniques to overcome the challenges of current chip architectures.
Since the 1960s, ensuring that electronics can handle more demanding applications has meant making transistors smaller so more can be packed onto a single chip. But, as Cao pointed out, doubling the number of transistors every couple of years — a principle known as Moore's law — is becoming less feasible.
"This is because we're becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we're going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface."
"Today it takes six microelectronic devices called transistors on a single plane to store one bit of information," Cao explained, suggesting that just like in a densely populated city, the only way to solve overcrowding is to build upward. "You get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient."
Scientist Gordon Moore seen with a graph representing Moore's Law. (Image credit: Intel)Getting around the heat problem
However, once the first chip layer has been completed, the metal wiring introduced to connect further layers can be destroyed by such high temperatures. As a result, the "thermal budget" — the maximum amount of heat that can be endured before degradation starts to occur — for any additional layers is 752 F (400 C), said Cao. This can result in performance and reliability issues.
To overcome this challenge, Cao and his team adopted an approach called "monolithic integration" — a process in which all chip components are fabricated on a single piece of substrate, as opposed to making them separately and then bonding them together later.
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The result of this process was a 3D chip with three layers, each containing 625 transistors. This pales in comparison to the billions of transistors that can be crammed onto chips already on the market, but the researchers believe their technology boasts power efficiency benefits. The electrical current that can flow through the chip has proved to be at least three to four times greater than that of monolithic chips made from alternative materials.
Can you match these ancient devices to their pictures? Find out with our computing quiz!
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